1. Technical Field
The present invention generally relates to multi-level cell (MLC) flash memory and, more particularly, to a circuit for sensing an MLC flash memory.
2. Background
A multi-level cell (MLC) refers to a memory cell having a plurality of threshold voltages. To detect the threshold voltage of an MLC, a sensing circuit needs to decode multi-bit data that represent the threshold voltages. FIG. 1 is a circuit diagram of a circuit 10 for sensing an MLC flash memory in prior art. Referring to FIG. 1, the circuit 10 includes decoding units 11 to 14, wherein a cell voltage Vcell in the decoding unit 11 is compared with voltages Vref1, Vref2 and Vref3 in the decoding units 12, 13 and 14, respectively so that multi-bit data can be decoded at a sense amplifier (SA) decoder 106.
FIG. 2 is a circuit diagram of another circuit 20 for sensing an MLC flash memory in prior art. Referring to FIG. 2, the circuit 20 includes a ramp generator 201 and decoding units 21 to 24. The ramp generator 201 provides a ramp signal to the decoding units 21 to 24. Latches 202 latch outputs from the decoding units 21 to 23 at different latch time points so that multi-bit data can be decoded at a decoder 203. FIG. 3 is a schematic diagram showing an exemplary ramp signal for sensing multi-bit data.
The above-mentioned circuits 10 and 20 may be complex and take up a large area, and may have low response speed or large power consumption. It may thus be desirable to have a circuit that can address the issues of the prior art circuits.